RT-XSG

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RT-XSG

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Ultrafast Models and I/Os Configuration

RT-XSG offers ready to use Simulink function blocks for FPGA Hardware-in-the-Loop and Rapid Control Prototyping simulation. It also manages the configuration of the FPGA, as well as the transfer of high-bandwidth data between real-time RT-LAB and HYPERSIM simulation models and the user-defined custom system running on the FPGA.


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Product Features

The RT-XSG toolbox allows for FPGA target code to be included as part of a larger real-time simulation model. The model includes all parts of the simulation while FPGA HDL code is automatically generated and dispatched by RT-XSG. It enables the fast creation of FPGA HDL without knowledge of the language.


RT-LAB-XSG-schema_Final-2

 

Fully Integrated with XILINX System Generator for DSP™

While conventional processor designs operate sequentially on a set of instructions, FPGA processors perform operations in parallel. This makes them ideally suited for very fast simulation of loosely-coupled models. Some examples of applications already implemented using RT-XSG are:

  • High-speed digital and/or analog waveform generators (resolver, encoder, PWM, sine, SPI, etc)

  • Signal processing, windowing and analysis

  • Embedded simulation of stiff (high-speed dynamics) models, such as electrical motor and power converter models

  • Timing analysis

Xilinx-System-Generator

 

 

Product Benefits

Facilitate FPGA Programming

The RT-XSG library contains several function blocks for FPGA programming similar to MATLAB Simulink function.

 

Flexibility

The user has the freedom to generate a custom, application specific model to be implemented onto the FPGA device. RT-XSG blockset provides signal conditioning and conversion modules that can then be attached to the custom model for real-time, hardware-in-the-loop data processing.

 

Powerful

While RT-LAB allows the user to distribute the computation of a complex plant or controller model on multiple computation nodes based on PC hardware, RT-XSG uses dedicated FPGA processors for sub-microsecond computation loops.